Integrated circuits are connectable to “the outside world” through input nodes, output nodes, or input/output nodes such as bond pads, input pads, input/output pins, die terminals, die pads, or contact pads. Circuitry is often interposed between such nodes and active circuitry of the integrated circuit. The circuitry typically includes transistors which should be protected from over-limit electrical conditions. This may be especially true for circuits that include field-effect transistors (FETs), which are formed having a gate insulator. An uncontrolled over-limit electrical event may subject the gate insulator to a relatively high voltage that exceeds a breakdown voltage that causes permanent damage to the transistor.
An electrostatic discharge event during which the circuitry is subjected to an electrostatic discharge (ESD) is an example of an over-limit electrical condition that may cause damage to the circuitry of the integrated circuit unless adequately protected. Another example of an over-limit electrical condition for example, latch-up, may result from an “overdrive condition,” An overdrive condition exists when voltages or currents at an electrical node exceed specified levels, such as a manufacturer's specification of the “normal” operating parameters for the device. Overdrive conditions can be contrasted with what is typically referred to as a normal operating conditions, that is, conditions specified by a semiconductor device manufacturer to be within specified limits. Circuitry subjected to an overdrive condition may conduct current inadvertently and without control over the current path or the magnitude of current conducted. It is desirable, however, that circuitry is designed to withstand an occasional or even sustained overdrive condition without adverse consequences. Uncontrolled overdrive conditions, in contrast, may cause over-limit electrical conditions that may damage circuitry, and consequently, should be avoided.
Typically, an over-limit protection circuit is connected to a node, such as a bond pad, that may be subjected to an over-limit electrical condition in order to protect circuitry also coupled to the node. Typical over-limit electrical condition protection circuits include circuitry that provide a low-impedance conductive path from the node to a reference voltage, such as ground, to dissipate the over-limit electrical condition before operational circuitry also coupled to the node are damaged. For example, the over-limit protection circuit keeps the potential of the bond pad from exceeding a maximum value.
Many of the protection circuits include circuits that exhibit a “snap-back” characteristic. Generally, a snap-back characteristic provides a trigger condition which when exceeded, causes the circuit to enter a low-impedance state. The low-impedance state is maintained while the electrical condition on a node exceeds a hold condition. In designing an adequate protection circuit using a snapback circuit, the trigger condition for the snapback circuit must be appropriate for the electrical conditions the node will experience under normal operating conditions. For example, the trigger conditions should be sufficiently high to prevent the protection circuit from inadvertently triggering but low enough to trigger before operational circuitry coupled to the node are subjected to damaging over-limit electrical conditions. An example of a node that will be subjected to relatively high voltages during normal operation are high-voltage (HV) pads which are used to provide circuitry relatively high-voltages during normal operation. Over-limit protection circuitry for such pads should be designed to avoid triggering when the expected operating voltage is provided to the pad but nonetheless trigger at an over-limit electrical condition below that which will damage circuitry coupled to the pad.
Examples of conventional circuits having snapback characteristics include thyristors, such as silicon controlled rectifiers (SCRs), and overdriven metal-oxide-semiconductor (MOS) transistors, and diodes. Examples of conventional circuits having a set trigger condition, and typically a set hold condition as well, include diode-triggered SCRs (DTSCRs). Once set, however, adjusting (e.g. changing, altering, etc.) the trigger condition often requires redesign of the protection circuit. That is, the protection circuits are typically “hard-wired” and are not modified after the integrated circuit is fabricated. Moreover, trigger conditions for ESD protection and protection against latch-up conditions are often different, thus, having a protection circuit having a trigger condition set to protect against one condition may be a compromise for protecting against the other over-limit electrical conditions.